I2C Bit Sampler
Serial communication protocols require robust data recovery in noisy environments. The I2C bit sampler extracts synchronous data bits from an asynchronous bus by monitoring the clock line.
The circuit operates on a high-speed system clock. It must monitor the I2C clock scl to detect a rising edge. When a rising edge is detected (i.e., scl transitions from 0 to 1), the circuit must wait exactly one system clock cycle to allow the data line to settle. On the following system clock cycle, it must sample the I2C data line sda and shift this bit into the least significant bit of an 8-bit shift register data_out.
When the synchronous active-high reset rst is asserted, data_out must be cleared to 0. Assume scl and sda are already synchronized to the system clock.
Constraints
- Use a synchronous active-high reset.
- Shift new data into the least significant bit (LSB) and shift existing bits left.
- Delay the capture of
sdaby exactly one clock cycle after thesclrising edge is detected.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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