Clock-to-Q Delay

EasyLogic CircuitTiming Diagram

A positive-edge-triggered D flip-flop with a non-ideal clock-to-Q delay updates its output $t_{pcq}$ time steps after the rising edge of the clock.

Three signals are evaluated: CLK (clock), D (input) and Q (output). The delay $t_{pcq}$ is exactly 4 time steps and Q is initially 0.

Trace the value of Q across all 16 time steps.

Constraints

The output Q must transition exactly 4 time steps after the positive clock edge.
The value captured from D is evaluated exactly at the rising edge of CLK.
Changing Q synchronously at the clock edge produces incorrect hold time analysis for downstream logic and is considered incorrect.

TimingLatches and Flip-FlopsClock-to-Q

Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

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