Setup and Hold Time Windows: Waveform Annotation
A timing violation detector evaluates the stability of input D relative to the positive edge of CLK.
Three signals are shown: CLK (clock, rising edge at t=10), D (data input), and ERR (violation output, initially 0). The target flip-flop has a setup time of 3 time steps and a hold time of 2 time steps.
Trace ERR across all 16 time steps: set ERR to 1 only at the exact time steps where D changes state within the setup window (t=7 through t=9) or the hold window (t=10 through t=11).
Constraints
ERRis evaluated at each time step independently and does not hold its value.- A transition occurs at the exact time step where the
Dvalue differs from the previous time step.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.