Maximum Clock Frequency: T_min Computation
Synchronous digital systems rely on strict timing boundaries to guarantee that data propagates and stabilizes before the next clock edge arrives.
The circuit shown consists of two flip-flops, FF1 and FF2, separated by a block of combinational logic. The timing parameters provided are clock-to-Q delay t_pcq = 3 ns, maximum combinational logic delay t_comb = 8 ns, minimum combinational logic delay t_comb_min = 2 ns, setup time t_setup = 2 ns, and hold time t_hold = 4 ns.
Determine the minimum clock period T_min, the maximum clock frequency f_max, and verify whether the circuit meets the hold time constraint.
Constraints
- Assume zero clock skew and zero clock jitter.
- All time values are in nanoseconds (ns).
- Frequency answers must be expressed as exact fractions in GHz.
Topics
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