Setup Time Constraint: Maximum Allowed Combinational Delay
Clock frequency dictates the maximum depth of combinational logic between pipeline stages in synchronous digital systems.
A synchronous circuit contains two positive-edge triggered D flip-flops, FF1 and FF2, connected by a combinational logic block. The clock period T_period is 10 ns. Both flip-flops share the same clock and have a clock-to-Q delay t_pcq of 2 ns and a setup time t_setup of 1.5 ns. The combinational logic block contains three parallel paths: Path_A with a delay of 5 ns, Path_B with a delay of 6 ns, and Path_C with a delay of 7 ns.
Calculate the maximum allowable combinational delay t_comb_max for this pipeline stage. Evaluate the existing paths to determine which ones meet the timing criteria and which require optimization.
Constraints
- All time units are evaluated in nanoseconds (ns).
- Clock skew and clock jitter are assumed to be zero.
- Hold time constraints are assumed to be met.
Topics
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