DFF: Hold Time Violation
A positive-edge-triggered D flip-flop requires its input to be stable during specific setup and hold windows around the clock edge to avoid metastability.
The setup window is the one time step immediately preceding the rising edge of CLK. The hold window is the exact time step of the rising edge. If D transitions during either window, the output Q becomes indeterminate ("X").
Three signals are shown: CLK (clock, period 4), D (input), and Q (output, initially 0).
Trace Q across all 16 time steps.
Constraints
- Output
Qonly updates on the rising edge ofCLK(time steps 2, 6, 10, and 14). - A hold time violation occurs if
Dchanges at the exact time stepCLKtransitions to 1. - Slowing the clock frequency does not fix hold violations: only adding delay to the data path resolves them.
Topics
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