Critical Path: 4-Stage Pipeline Identification
A 4-stage pipeline processes a signal IN through four sequential stages. Each stage consists of a combinational logic block followed by a positive-edge-triggered D flip-flop. The combinational delays for stages 1 through 4 are 5 ns, 12 ns, 8 ns, and 11 ns respectively. All flip-flops have a clock-to-Q delay ($t_{pcq}$) of 2 ns and a setup time ($t_{setup}$) of 1 ns. The clock signal CLK has a period of 14 ns (represented by two time steps). If a stage's total required time ($t_{pcq} + t_{comb} + t_{setup}$) exceeds the clock period, it fails to meet setup time and instead captures the stable value from the previous clock cycle, effectively acting as a 2-cycle delay.
Three signals are shown: CLK (clock, period 2 steps), IN (pipeline input), and S4 (output of the final stage, initially 0).
Trace S4 across all 22 time steps.
Constraints
- Calculate the absolute minimum clock period required for each individual stage.
- Stages that meet the 14 ns timing constraint propagate data with a 1-cycle latency.
- Stages that violate the timing constraint propagate data with a 2-cycle latency.
Topics
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