Clock Skew: Effect on Timing Margin
Clock distribution networks in physical silicon cannot deliver active edges to all flip-flops exactly simultaneously.
The circuit analyzed contains two sequential elements, FF1 (launch) and FF2 (capture), separated by a combinational logic block. The clock signal CLK_capture arrives at FF2 exactly 1 time unit earlier than CLK_launch arrives at FF1. The clock period is designated as T_period. The flip-flops have a clock-to-Q delay of t_pcq, a setup time of t_setup, and a hold time of t_hold. The combinational logic has a maximum delay of t_comb_max and a minimum delay of t_comb_min.
Determine the maximum allowable combinational delay and evaluate the hold time risk under different skew conditions.
Constraints
- All time values are strictly positive.
- Clock jitter is assumed to be zero for this analysis.
- Setup and hold times are relative to the active clock edge at the specific flip-flop's clock pin.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.