Metastability: D Transition Inside Setup-Hold Window
A positive-edge-triggered D flip-flop enters an indeterminate metastable state if its input transitions simultaneously with the active clock edge, violating setup and hold requirements.
Three signals are shown: CLK (clock, period 2), D (input), and Q (output, initially 0).
Trace Q across all 8 time steps, using the value "X" for any period where the output is metastable.
Constraints
- Use the character "X" (capitalized) to denote any time step where the output state is indeterminate.
- Assume the flip-flop resolves to a valid logic level on the next positive clock edge where setup and hold times are successfully met.
- The flip-flop holds its current state (valid or metastable) while the clock is LOW.
Topics
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