Counter: Lockup Detection Output Signal
System watchdogs monitor critical state machines and counters to ensure they do not freeze during operation. A lockup detector flags when a sequential element remains in the identical state across multiple clock cycles, allowing a microcontroller to trigger a reset or alert.
Construct a lockup detection circuit for a 4-bit counter. The circuit receives the current counter state via inputs Q3, Q2, Q1, and Q0. It must register these inputs on every clock cycle to maintain a record of the previous state. The output LOCKUP must be driven HIGH continuously whenever the current state exactly matches the registered previous state. A synchronous active-high rst signal must clear the registered previous state to 0.
| Q == Q_prev | LOCKUP | |---------------|----------| | 0 | 0 | | 1 | 1 |
Constraints
- Use exactly four D flip-flops to store the previous state.
- Implement the state comparison using only basic combinational logic gates.
- Do not use high-level equality comparator blocks: build the bitwise comparison manually.
- The
rstsignal must synchronously clear all flip-flops to 0.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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