Counter: Maximal Valid Sequence Design (15 of 16 States)
Modulo-N counters frequently align to non-power-of-two boundaries in timing circuits and frequency dividers. A modulo-15 counter maximizes the state utilization of a 4-bit register while reserving a single state for error detection or synchronization.
The circuit must implement the combinational next-state logic for a 4-bit synchronous up-counter. The current state is provided via inputs Q3, Q2, Q1, and Q0. The circuit must generate the next state on outputs D3, D2, D1, and D0. The counter increments by one for all states from 0 to 13. State 14 transitions to state 0. If the counter enters the invalid state 15, it must recover by transitioning directly to state 0.
| Q3 | Q2 | Q1 | Q0 | D3 | D2 | D1 | D0 | |------|------|------|------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
Constraints
- Implement only the combinational next-state logic.
- Do not use any sequential elements like flip-flops or latches.
- Handle the invalid state 15 explicitly: it must route to state 0.
Topics
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