Counter: Self-Correcting but Skips Valid State Debug
A modulo-6 counter tracks sequences from 0 to 5 and must safely recover to 0 if an invalid state is reached. The next-state logic block computes the subsequent state N2, N1, N0 based on the current state Q2, Q1, Q0.
Expected behavior:
| Q2 | Q1 | Q0 | N2 | N1 | N0 | |------|------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 1 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | 1 | 1 | | 0 | 1 | 1 | 1 | 0 | 0 | | 1 | 0 | 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 0 | 0 | 0 | | 1 | 1 | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 0 | 0 | 0 |
Simulation shows N2=1, N1=0, N0=1 for input Q2=1, Q1=1, Q0=0. The self-correction logic forces the counter into state 5 instead of state 0, skipping valid states 0 through 4 on the first post-recovery cycle. Inspect the circuit and correct the fault.
Constraints
- Do not alter the logic paths that govern the valid count sequence.
- Use only standard combinational logic gates.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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