Counter: Worst-Case Recovery Time for Multi-State Invalid Chain
Mission-critical hardware must guarantee predictable recovery times when radiation or power glitches force a state machine into an unmapped state.
The system below uses a 4-bit synchronous counter with states 0 through 9 forming the valid counting sequence. The synthesis tool optimized the logic using don't-cares for the invalid states 10 through 15. The resulting next-state transitions for the invalid states are defined as follows: 10 transitions to 11, 11 transitions to 0, 12 transitions to 13, 13 transitions to 14, 14 transitions to 0, and 15 transitions to 0.
Trace the recovery paths for all unmapped states. Determine the longest possible recovery sequence and identify the maximum number of clock cycles required to return to a valid state.
Constraints
- Valid states are
0through9. - All state transitions occur on the rising edge of the system clock.
- Recovery is considered complete the moment the counter enters any valid state.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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