Self-Correction with Synchronous Load
State machines in aerospace and automotive applications must recover from single-event upsets without ignoring external commands. A counter with both self-correction and synchronous load requires strict priority resolution to ensure external control is never locked out by internal error handling.
Design a 3-bit Modulo-5 counter that counts continuously from 0 to 4. The circuit has a 1-bit control signal LOAD, a 3-bit data input D, and a 3-bit output Q. The design must enforce a strict priority hierarchy: synchronous loads override self-correction, and self-correction overrides the normal count sequence.
| LOAD | Current Q | Next Q | Behavior | |--------|-------------|----------|----------| | 1 | Any | D | Synchronous load overrides all other logic | | 0 | 0, 1, 2, 3 | Q + 1 | Normal count | | 0 | 4 | 0 | Normal wrap around | | 0 | 5, 6, 7 | 0 | Self-correction to valid state |
Constraints
- Implement the design using only standard combinational logic gates and D flip-flops.
- Trigger all state transitions on the positive edge of the clock.
- Do not use high-level behavioral counter blocks or macro-cells.
- Resolve all priority conflicts purely through combinational next-state logic.
Topics
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