Johnson Counter: Self-Correction for 2-State Lockup Cycle
Uncorrected Johnson counters can become permanently trapped in invalid state cycles due to noise or power-up glitches. The most notorious trap is the 1010 state, which requires dedicated detection logic to force a safe recovery.
Design a self-correcting 4-bit Johnson counter. The circuit must follow the standard Johnson sequence, but if it enters the invalid 1010 state, it must synchronously clear to 0000 on the next clock edge. A synchronous load input is provided to inject specific states for testing.
Behavioral Specification: * When rst is 1: Q synchronously clears to 0000. * When rst is 0 and load is 1: Q synchronously loads D_in. * When rst is 0 and load is 0: * If Q equals 1010: Q synchronously clears to 0000. * For all other states: Q performs a standard Johnson shift where Q[3] receives ~Q[0], and Q[2:0] receives Q[3:1].
| Port | Direction | Width | Description | |------|-----------|-------|-------------| | clk | Input | 1-bit | Clock signal | | rst | Input | 1-bit | Synchronous reset (active high) | | load | Input | 1-bit | Synchronous load enable | | D_in | Input | 4-bit | Data input for state injection | | Q | Output | 4-bit | Counter state output |
Constraints
- Implement the state register using D flip-flops.
- Trigger all state transitions and corrections synchronously on the clock edge.
- Detect the
1010state using only combinational logic gates. - Do not use asynchronous resets to clear the
1010state.
Topics
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