Mod-9 Counter: Self-Correction Verification
A hardware engineer is testing the self-correction logic of a positive-edge-triggered Mod-9 counter: the counter synchronously resets to 0000 if Q3 AND Q0 is HIGH, increments its state by 1 otherwise, or loads D[3:0] if LOAD is HIGH.
Six input signals are shown: CLK (clock, period 2), LOAD (active-high load enable), and D3, D2, D1, D0 (data inputs).
Trace the four output signals Q3, Q2, Q1, and Q0 (initially 0000) across all 16 time steps to verify which invalid states successfully recover in one cycle and which fail.
Constraints
- Output transitions occur only on the LOW-to-HIGH edge of
CLK. - The reset condition (
Q3 AND Q0) is evaluated based on the current state immediately before the clock edge. - The
LOADsignal takes priority over both the increment and reset behaviors.
Topics
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