Self-Correcting Counter: State 3 Recovery
High-reliability state machines must recover predictably from single-event upsets. A modulo-5 counter typically resets to zero upon entering an invalid state, but specific protocol timings often demand a non-zero recovery target to maintain synchronization.
Design the combinational next-state logic for a 3-bit modulo-5 counter. The valid counting sequence is 0 to 4. If the current state is invalid (5, 6, or 7), the next state must immediately evaluate to 3 (011).
| Q2 | Q1 | Q0 | D2 | D1 | D0 | |------|------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 1 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | 1 | 1 | | 0 | 1 | 1 | 1 | 0 | 0 | | 1 | 0 | 0 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | 1 | 1 | | 1 | 1 | 0 | 0 | 1 | 1 | | 1 | 1 | 1 | 0 | 1 | 1 |
Constraints
- Implement combinational logic only.
- Do not use sequential elements like flip-flops or latches.
- Drive all output bits explicitly for every input combination.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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