D Latch: Asynchronous Preset and Clear Inputs
Standard logic families like the 74xx series require reliable initialization states upon power-up or during system reset. Asynchronous preset and clear signals override the normal data path to force the latch into a known state instantly.
Construct a D latch with active-low preset (PRE_bar) and clear (CLR_bar) inputs. When both asynchronous controls are high, the circuit operates as a standard transparent latch controlled by EN and D. When PRE_bar is low, the output Q is forced to 1. When CLR_bar is low, the output Q is forced to 0. These overrides must function regardless of the state of EN or D.
| PRE_bar | CLR_bar | EN | D | Q | Q_bar | |-----------|-----------|------|-----|-----|---------| | 0 | 1 | X | X | 1 | 0 | | 1 | 0 | X | X | 0 | 1 | | 1 | 1 | 1 | 0 | 0 | 1 | | 1 | 1 | 1 | 1 | 1 | 0 | | 1 | 1 | 0 | X | Q | Q_bar |
Constraints
- Implement using only basic logic gates (NAND, NOR, AND, OR, NOT).
- Do not use pre-built latch or flip-flop primitives.
- The preset and clear functions must be strictly asynchronous.
Topics
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