D Latch vs. D Flip-Flop
A level-sensitive D latch passes D to Q_LATCH while CLK is HIGH and holds its value when LOW, whereas a positive-edge-triggered D flip-flop captures D to Q_DFF only on the LOW-to-HIGH transition of CLK. Four signals are shown: CLK (clock/enable), D (input), Q_LATCH (output, initially 0), and Q_DFF (output, initially 0). Trace both Q_LATCH and Q_DFF across all 12 time steps to observe how they diverge when D changes mid-cycle.
Constraints
- The outputs must reflect ideal behavior with zero propagation delay.
- Evaluate the inputs strictly at the current time step.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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