D Latch: Permanently-Enabled Latch Debug
A D latch stores a single bit of data for temporary holding in memory registers.
Expected behavior:
| EN | D | Q (next) | |------|-----|------------| | 0 | 0 | Q (prev) | | 0 | 1 | Q (prev) | | 1 | 0 | 0 | | 1 | 1 | 1 |
Simulation shows Q = 1 for inputs EN=0, D=1 immediately following a state where Q=0. The output tracks the data input continuously and fails to hold its state. Inspect the circuit and correct the fault.
Constraints
- Do not replace the entire latch component
- Only modify the wiring to restore the correct enable control logic
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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