Debug Sequential: Johnson Counter Feedback Inversion
A 4-bit Johnson counter generates a specific sequence of states by feeding the inverted output of the final shift register stage back to the input of the first stage.
Expected behavior:
| CLK cycle | Q0 | Q1 | Q2 | Q3 | |-------------|------|------|------|------| | 0 (Reset) | 0 | 0 | 0 | 0 | | 1 | 1 | 0 | 0 | 0 | | 2 | 1 | 1 | 0 | 0 | | 3 | 1 | 1 | 1 | 0 | | 4 | 1 | 1 | 1 | 1 | | 5 | 0 | 1 | 1 | 1 | | 6 | 0 | 0 | 1 | 1 | | 7 | 0 | 0 | 0 | 1 | | 8 | 0 | 0 | 0 | 0 |
Simulation shows that after reset, the counter remains at state Q0=0, Q1=0, Q2=0, Q3=0 for all subsequent clock cycles. The shift register fails to fill with 1s. Inspect the circuit and correct the fault.
Constraints
- Do not add new flip-flops or registers to the circuit.
- Only modify the existing feedback logic or wiring to restore the correct sequence.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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