DFF: Propagation Delay Accumulation in 4-FF Ripple Chain
A 4-stage shift register connects four positive-edge-triggered D flip-flops in series (IN to FF1, Q1 to FF2, Q2 to FF3, Q3 to FF4) with no combinational logic between stages. In a zero-delay ripple chain, the propagation delay (t_pcq) of one stage must satisfy the hold time (t_hold) of the next stage to prevent metastability.
Six signals are shown: CLK (clock), IN (input to FF1), and the stage outputs Q1, Q2, Q3, and Q4 (all initially 0).
Trace Q1, Q2, Q3, and Q4 across all 16 time steps.
Constraints
- A clock edge occurs at the exact time step
CLKtransitions from 0 to 1. - Flip-flop outputs update
t_pcq = 2time steps after a clock edge. - An input must remain stable during the clock edge step and the subsequent
t_hold - 1steps (for a total oft_hold = 3steps) to satisfy the hold constraint. - If an input changes during the hold window, the flip-flop output becomes unknown ("X")
t_pcqsteps after the clock edge. - Assume
INalways satisfies setup and hold constraints forFF1.
Topics
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