DFF: Reset Priority vs. Data Priority
A positive-edge-triggered D flip-flop with synchronous reset enforces reset priority over data input through conditional logic in the data path. On every LOW-to-HIGH transition of CLK, the output Q becomes 0 if RST is 1, otherwise it captures the value of D.
Four signals are shown: CLK (clock, period 2), RST (synchronous reset input), D (data input), and Q (output, initially 0).
Trace the output Q across all 10 time steps.
Constraints
- The output
Qonly changes state exactly at the LOW-to-HIGH transition ofCLK. - Synchronous reset means
RSTis only evaluated at the clock edge, not continuously. - If both
RSTandDare asserted at the same clock edge, reset wins.
Topics
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