T Flip-Flop: Construction from DFF via Excitation Equation
Counters and frequency dividers rely on state elements that toggle their output on command. Standard cell libraries often lack native toggle flip-flops, requiring designers to synthesize them using standard D-type flip-flops and combinational logic.
Construct a T (Toggle) flip-flop using a single D flip-flop and basic logic gates. The output Q must invert its current state on the rising edge of clk when T is 1, and retain its current state when T is 0.
To determine the combinational logic required at the D input, use the following excitation table mapping the current state and T input to the required next state:
| T | Q (current) | Q_next (required D) | |-----|---------------|-------------------------| | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 0 |
Constraints
- Use exactly one D flip-flop.
- Use exactly one combinational logic gate to compute the D input.
- Do not use any other sequential elements or latches.
Topics
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