DFF: Setup and Hold Violations
A positive-edge-triggered D flip-flop updates Q on the LOW-to-HIGH transition of CLK (step $E$), but enters a metastable state (X) if D transitions at step $E-1$, $E$, or $E+1$.
Three signals are shown: CLK (clock, period 4), D (input), and Q (output, initially 0). A transition at step $T$ means the value at $T$ differs from the value at $T-1$.
Trace Q across all 24 time steps, using X for any cycles where a setup or hold violation occurs.
Constraints
Qupdates only at the exact stepCLKtransitions from 0 to 1.- Metastability (
X) persists until the next valid LOW-to-HIGH clock transition successfully captures a stableD.
Topics
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