Two DFFs in Series: Pipeline Latency
Two positive-edge-triggered D flip-flops are connected in series to form a two-stage pipeline where each flip-flop captures its input on the LOW-to-HIGH transition of the shared clock.
Four signals are shown: CLK (clock, period 2), D1 (input to the first stage), Q1 (output of the first stage, initially 0), and Q2 (output of the second stage, initially 0).
Trace Q1 and Q2 across all 12 time steps.
Constraints
- The output
Q1updates to matchD1only at the rising edge ofCLK. - The output
Q2updates to match the pre-edge value ofQ1only at the rising edge ofCLK. - Changes to
D1between clock edges do not affect the outputs until the next rising edge.
Topics
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