DFF with Clock Enable
Power-saving techniques and pipeline stalls require registers to hold their state across multiple clock cycles. Directly gating the clock network introduces dangerous clock skew and glitches, so designers use a synchronous clock enable pattern to conditionally recirculate the current state.
The circuit must capture the input D on the rising edge of clk only when CE is high. When CE is low, the circuit must ignore D and hold its current value Q.
| CE | D | Q_next | |------|-----|----------| | 0 | 0 | Q | | 0 | 1 | Q | | 1 | 0 | 0 | | 1 | 1 | 1 |
Constraints
- Use exactly one D flip-flop.
- Use exactly one 2:1 multiplexer.
- Do not connect any logic gates to the
clksignal path. - Connect the
clkinput directly to the clock pin of the flip-flop.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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