DFF: Setup Time Violation
A positive-edge-triggered D flip-flop captures the value of D on the LOW-to-HIGH transition of CLK provided D is stable immediately before the edge. Three signals are shown: CLK (clock, period 2), D (input) and Q (output, initially 0). If D transitions at the exact same time step as the CLK rising edge, a setup time violation occurs and Q becomes indeterminate ('X'). Trace Q across all 10 time steps.
Constraints
- The output must be exactly 0, 1, or "X" for each time step.
- Use "X" to represent a metastable state caused by a setup time violation.
- The flip-flop holds its previous state (including "X") when the clock is LOW.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.