Divide by 8 with 50 Percent Duty Cycle
Many analog components and memory interfaces require strict 50 percent duty cycles to function correctly. A divide-by-8 circuit generates a symmetric slow clock from a high-speed reference.
The circuit must track the number of clock cycles and output a square wave on clk_out. The output frequency must be exactly one-eighth of the input clock frequency. To maintain a 50 percent duty cycle, clk_out must remain low for four cycles and high for four cycles. When the synchronous active-high rst is asserted, the internal counter must clear and clk_out must be driven to 0.
| rst | internal state | clk_out | |-------|----------------|-----------| | 1 | 0 | 0 | | 0 | 1 | 0 | | 0 | 2 | 0 | | 0 | 3 | 0 | | 0 | 4 | 1 | | 0 | 5 | 1 | | 0 | 6 | 1 | | 0 | 7 | 1 | | 0 | 0 | 0 |
Constraints
- Implement using a synchronous 3-bit counter.
- The
rstsignal must be synchronous and active-high. - Do not use latches or asynchronous resets.
Topics
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