Power of 2 Divider Chain
System-on-Chip architectures often require a hierarchy of related clocks to drive different buses and peripherals at scaled frequencies. Generating these clocks synchronously ensures they maintain strict phase alignment across the die.
The circuit must generate three divided clock signals. The outputs div2, div4, and div8 must divide the primary clock frequency by 2, 4, and 8 respectively. To prevent timing violations between clock domains, all divided outputs must transition simultaneously on the rising edge of the clock with zero relative phase skew. A high rst signal synchronously resets all outputs to 0.
| Cycle | rst | div8 | div4 | div2 | |-------|-------|--------|--------|--------| | 0 | 1 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 1 | | 2 | 0 | 0 | 1 | 0 | | 3 | 0 | 0 | 1 | 1 | | 4 | 0 | 1 | 0 | 0 | | 5 | 0 | 1 | 0 | 1 | | 6 | 0 | 1 | 1 | 0 | | 7 | 0 | 1 | 1 | 1 | | 8 | 0 | 0 | 0 | 0 |
Constraints
- Drive all flip-flops using only the primary clock signal.
- Do not cascade the output of one flip-flop into the clock pin of another.
- Implement an active-high synchronous reset using the
rstsignal.
Topics
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