Duty Cycle Comparator
Decoding Pulse Width Modulation (PWM) signals requires distinguishing between logical symbols based on their duty cycle. A common technique in infrared and RF receivers compares the duration of the high phase to the low phase over a fixed period.
The circuit evaluates the pwm_in signal over a period marked by the period_end strobe. When period_end is high, the circuit must output high_dominant as 1 if pwm_in was high for a greater or equal number of clock cycles than it was low during the current period, and 0 otherwise. The high_dominant output must hold its evaluated state until the next period_end strobe. The evaluation period includes the cycle where period_end is high. Upon rst, high_dominant must be 0 and the internal count must reset.
Constraints
- Use a single up/down counter.
- Do not instantiate separate counters for high and low durations.
- Extract the comparison result directly from the counter's sign bit.
- Reset the counter synchronously when
period_endis asserted to start fresh for the next period.
Topics
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