Period Measurement
Tachometers, frequency counters, and clock recovery circuits rely on precise timing measurements of incoming waveforms. Measuring the period of an unknown signal requires counting reference clock cycles between consecutive rising edges.
The circuit tracks the number of system clock cycles between rising edges of sig_in. An internal 8-bit counter increments by one every clock cycle. When a synchronous rising edge is detected on sig_in, the circuit must output the current counter value on period, assert the valid signal for exactly one clock cycle, and synchronously reset the counter to zero to begin the next measurement. The period output must hold its most recent measurement until a new measurement is ready. When rst is high, the counter resets to zero, period becomes zero, and valid is deasserted.
Constraints
- Use synchronous reset logic exclusively.
- The
periodoutput must be exactly 8 bits wide. - The
validoutput must be 1 bit wide and assert for only one cycle per detected edge. - Do not reset the counter if
sig_inremains high: only reset on the transition from low to high.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.