Pulse Width Capture Register
Pulse width modulation receivers and frequency counters require stable data for downstream processing. A capture register holds a fleeting measurement while the system prepares for the next incoming pulse.
The circuit must monitor the 1-bit pulse signal and detect its falling edge. When a falling edge occurs, it must store the current 8-bit count_in value into the 8-bit capture_out register. Simultaneously, it must assert the 1-bit valid signal to notify downstream logic that new data is available.
Behavioral requirements: * Synchronous updates occur on the rising edge of the 1-bit clk signal. * When the 1-bit rst signal is 1, capture_out is reset to 0 and valid is forced to 0. * When pulse transitions from 1 to 0, capture_out updates with count_in and valid becomes 1 for exactly one clock cycle. * During all other conditions, capture_out retains its previous value and valid remains 0.
Constraints
- Implement using synchronous logic triggered by the rising edge of
clk. - Treat
rstas a synchronous, active-high reset. - The
validsignal must be registered and remain high for exactly one clock cycle per falling edge.
Topics
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