Maximum Pulse Width Timeout
Communication buses often rely on shared lines that can be pulled low by any device. If a node fails and holds the line low indefinitely, the entire bus hangs unless a watchdog timer detects the timeout and triggers a reset.
The circuit monitors a single input sig_in. When sig_in is high, the system is idle and the err_flag output remains 0. If sig_in drops low and remains low for more than 15 consecutive clock cycles, err_flag must assert high on the 16th cycle. The err_flag must immediately deassert to 0 on the next clock cycle where sig_in returns high.
Constraints
- Use sequential logic elements to track the elapsed cycles.
- Prevent the internal counter from wrapping around to zero if
sig_inremains low indefinitely. - Reset the internal counter synchronously whenever
sig_inis high.
Topics
Solve this problem
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