Minimum Pulse Width Validator
High-speed communication interfaces and control lines often suffer from wide noise spikes that bypass simple RC debouncers. A digital pulse width validator ensures signal integrity by rejecting any transient high state that fails to meet a strict duration threshold.
The circuit must monitor the input sig_in. When sig_in transitions from high to low, the output valid_pulse must assert for exactly one clock cycle if and only if sig_in was continuously high for at least 5 consecutive clock cycles immediately preceding the fall.
| Cycle | sig_in | valid_pulse | Note | |-------|----------|---------------|------| | 1 | 1 | 0 | Pulse begins | | 2 | 1 | 0 | | | 3 | 1 | 0 | | | 4 | 1 | 0 | | | 5 | 1 | 0 | 5th consecutive high cycle | | 6 | 0 | 1 | Pulse falls: valid | | 7 | 1 | 0 | New pulse begins | | 8 | 1 | 0 | | | 9 | 0 | 0 | Pulse falls: invalid (2 cycles) |
Constraints
- Implement synchronous logic triggered on the rising edge of the implied clock.
- Use an active-low asynchronous reset via
rst_n. - Output
valid_pulsemust remain high for exactly one clock cycle per valid event. - Do not assert
valid_pulsewhilesig_inis still high.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.