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Codiode/Problems/Sequential Logic

Phase Difference Measurement

HardLogic CircuitBuild

Time-of-flight applications like ultrasonic range finding and radar rely on precise measurement of the delay between a transmitted pulse and its received echo. A phase difference measurement unit captures this interval by timing the gap between two distinct asynchronous events.

The circuit must measure the number of clock cycles between the rising edge of sig_a and the rising edge of sig_b. An 8-bit output count increments by 1 each clock cycle while the measurement is active. The measurement begins on the clock cycle immediately following the rising edge of sig_a. The measurement ends on the clock cycle immediately following the rising edge of sig_b, holding the final count value. A 1-bit output active must remain high during the cycles where the measurement is in progress. If sig_b arrives before sig_a or at the exact same time, the event is ignored and the count remains 0. A 1-bit input rst clears the counter and resets the system to an idle state.

Constraints

  • Use an 8-bit unsigned integer format for the output count.
  • Do not increment the counter if sig_b transitions high before or simultaneously with sig_a.
  • Hold the final count value steady after sig_b arrives until a rst occurs.
  • Trigger all sequential logic on the rising edge of the clock.

Topics

countersstate-machinetimersradar

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