Pulse Train Counter
Particle detectors and frequency meters measure signal intensity by tallying discrete events over a fixed time interval.
When start is asserted, a measurement window opens for exactly 64 clk cycles. During this window, every cycle where pulse is high increments an internal counter. When the 64-cycle window closes, the circuit must assert valid and hold the accumulated count on the output until the next start signal or rst. Triggering start while a window is already open must be ignored.
Constraints
- Use only synchronous elements clocked by the main system
clk. - Do not route
pulseto any clock pins: it must be treated as a synchronous enable signal. - The
countoutput must be 7 bits wide to accommodate a maximum possible value of 64. - A synchronous
rstmust clear all internal counters and deassertvalid.
Topics
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