Frequency Limit Detector

Hardware systems must protect themselves from interrupt storms or mechanical contact bounces that escape early filtering stages. A frequency limit detector acts as a digital throttle: it enforces a strict minimum spacing between incoming events.

The circuit must monitor event_in for a rising edge (a transition from 0 to 1). When a rising edge is detected, the circuit evaluates the number of clock cycles elapsed since the most recent rising edge.

• If 10 or more clock cycles have elapsed, or if this is the first edge since reset: assert valid_event to 1 for exactly one clock cycle.
• If strictly fewer than 10 clock cycles have elapsed: assert error to 1 for exactly one clock cycle and keep valid_event at 0.
• The internal timer restarts its count on every rising edge of event_in, regardless of whether the event was flagged as valid or an error.

Outputs must remain 0 on clock cycles where no rising edge is detected.

Constraints

• Use a synchronous active-high rst signal.
• Evaluate the rising edge and assert the corresponding output in the same clock cycle that the 0-to-1 transition occurs.
• Do not increment the internal counter beyond the threshold required to validate the next event.

Topics

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