Edge Aligned Clock Divider
Communication frames often need a local clock tick that synchronizes phase with an incoming data stream. Generating a slow enable tick aligned to an external synchronization signal ensures data is sampled exactly at the center of the bit period.
Construct a divide-by-8 counter that outputs a single-cycle pulse on tick every 8 clock cycles. The counter must synchronously reset its phase whenever the external sync pulse arrives.
- When
rst_nis 0, the internal counter resets to 0. - When
syncis 1, the internal counter resets to 0 on the next clock edge. - Otherwise, the internal counter increments by 1 each clock cycle.
- The
tickoutput is 1 strictly when the internal counter equals 7, and 0 otherwise.
Constraints
- Implement synchronous active-low reset logic for
rst_n. - Reset the counter phase synchronously when
syncis asserted. - Drive
tickhigh for exactly one clock cycle per 8-cycle period.
Topics
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