Missing Pulse Detector
Reliable systems rely on a periodic heartbeat signal to confirm a subsystem is alive. A watchdog timer monitors this heartbeat and asserts a failure flag if the signal stops toggling.
The circuit must monitor an incoming pulse_in signal. An internal 2-bit counter increments by 1 on every clock cycle. A synchronous rising edge on pulse_in (a transition from 0 to 1) must reset this internal counter to 0. If the counter reaches its maximum value of 3, it must hold that value and the output missing_flag must assert high. The flag remains high until a new rising edge on pulse_in occurs or the active-high rst is asserted.
Constraints
- Implement an internal 2-bit counter that saturates at 3 instead of rolling over.
- Detect the rising edge of
pulse_insynchronously to the main clock. - Use an active-high synchronous reset
rstto clear the counter and the flag.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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