Synchronizer and Edge Detector Combo
External interrupts and physical button presses arrive asynchronous to the system clock. To trigger state machine transitions safely, these raw signals must be aligned to the clock domain before extracting a single-cycle pulse.
The circuit receives an asynchronous input async_in and outputs a synchronous signal pulse_out. The input must first pass through a two-stage flip-flop synchronizer to mitigate metastability. Following synchronization, the circuit must detect a rising edge on the synchronized signal and drive pulse_out high for exactly one clock cycle.
| Cycle | async_in | pulse_out | |-------|------------|-------------| | 1 | 0 | 0 | | 2 | 1 | 0 | | 3 | 1 | 1 | | 4 | 1 | 0 | | 5 | 0 | 0 |
Constraints
- Implement a two-stage synchronizer using strictly D flip-flops.
- Implement rising-edge detection exclusively on the synchronized signal, not the raw input.
- All flip-flops must be clocked by the same implicit system clock.
Topics
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