Endian Swapping Serializer
Communication bridges frequently translate between protocols with different bit-order conventions, such as SPI and UART. The endian-swapping serializer bridges these domains by dynamically reversing the transmission order based on a control signal.
The circuit accepts a 4-bit parallel input D and converts it to a serial output tx. A direction pin dir controls the shift direction.
Behavioral requirements: * When load is 1, the 4-bit input D is loaded into the internal register on the rising clock edge. * When load is 0, the register shifts its contents on each rising clock edge, shifting in 0s. * If dir is 1, the circuit operates in MSB-first mode. The tx pin outputs D[3], then D[2], D[1], D[0] on successive cycles. * If dir is 0, the circuit operates in LSB-first mode. The tx pin outputs D[0], then D[1], D[2], D[3] on successive cycles. * The tx output must reflect the current bit to be transmitted immediately after the clock edge.
Constraints
- Use D flip-flops for all state storage.
- Implement the shift logic using basic logic gates and multiplexers.
- Do not use pre-built serializer or shift register macros.
Topics
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