Basic Deserializer
Communication protocols like SPI and UART transmit data one bit at a time to reduce pin count. A deserializer reconstructs this serial stream into parallel words for internal processing.
The circuit must continuously shift the serial input din into a 4-bit parallel output dout. On every rising edge of the clock, the register shifts left: the current bits dout[2:0] move to dout[3:1], and din is sampled into dout[0]. An active-high synchronous rst clears all bits to 0.
Constraints
- Use only D flip-flops and basic logic gates.
- Implement a synchronous active-high reset.
- The shift operation must occur on every rising edge of the clock.
- The output
doutmust be strictly 4 bits wide.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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