Buffered Deserializer
Communication interfaces like UART and SPI receive data sequentially but hand it off to processors in parallel chunks. If the parallel output updates continuously during reception, downstream logic will read scrambled intermediate states.
The buffered deserializer shifts in a 1-bit din signal every clock cycle that en is high. A 3-bit internal counter tracks the number of shifts. On the 8th shift, the accumulated 8-bit word is transferred to a secondary holding register that drives the 8-bit dout signal. A 1-bit valid_out signal asserts for exactly one clock cycle when a new complete word is available on dout. The most significant bit is received first. Asserting rst clears all registers and sets the counter to 0.
Constraints
- Use only synchronous resets.
- Implement an internal 8-bit shift register and a separate 8-bit holding register.
- Update
doutonly when a full 8-bit word has been shifted in.
Topics
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