Sync Word Detector
Serial data links often lack a dedicated clock or frame start wire. The receiver must continuously hunt for a known synchronization pattern in the incoming bitstream to align bytes properly.
The circuit monitors a continuous single-bit input stream din. It must detect the 8-bit synchronization word 0xA5 (binary 10100101, received oldest bit first). When this exact sequence is present across the previous 8 clock cycles, the output sync_found must be asserted high for exactly one clock cycle.
| Cycle | din | sync_found | Note | |---|---|---|---| | 1 | 1 | 0 | | | 2 | 0 | 0 | | | 3 | 1 | 0 | | | 4 | 0 | 0 | | | 5 | 0 | 0 | | | 6 | 1 | 0 | | | 7 | 0 | 0 | | | 8 | 1 | 1 | Matches 10100101 |
Constraints
- Implement the design using only standard logic gates and D flip-flops.
- Treat
rstas a synchronous, active-high reset that clears all stored state. - Do not use pre-packaged shift register IP blocks.
Topics
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