Byte Aligned Deserializer
High-speed serial links transmit continuous bitstreams without word boundaries. The receiver must hunt for a known synchronization pattern to establish byte alignment before downstream logic can extract payloads.
The circuit receives a continuous serial bitstream on din. Upon reset, the system is unaligned and valid is 0. The circuit must monitor din for the 8-bit sync word 10100101 (received MSB first, meaning older bits are shifted left). Once this exact pattern is detected in the shift register, the receiver locks alignment. Starting exactly 8 clock cycles after the sync word is detected, and every 8 cycles thereafter, the circuit must assert valid high for one cycle. The dout port must continuously reflect the 8 most recently received bits.
Constraints
- Use a synchronous active-high reset
rst. - The
doutbus must update on every clock cycle regardless of the alignment state. - Once the sync word is found, the circuit must remain locked in alignment until a reset occurs.
- Do not assert
validwhen the sync word itself is detected: assert it for the payload bytes that follow.
Topics
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