Disparity Tracker
High-speed serial links like PCIe and Gigabit Ethernet rely on 8b/10b encoding to maintain DC balance across the transmission line. A running disparity tracker monitors the difference between transmitted ones and zeros to ensure the voltage does not drift.
The circuit evaluates a single transmitted bit din on each clock cycle and updates an internal disparity count. If din is 1, the disparity increments. If din is 0, the disparity decrements. The running total must clamp at a maximum positive disparity of +3 and a minimum negative disparity of -3.
The current disparity is output as disp, a 3-bit two's complement integer. A synchronous rst clears the disparity to 0.
| rst | din | Current disp | Next disp | |-------|-------|----------------|-------------| | 1 | X | X | 0 | | 0 | 1 | < 3 | disp + 1 | | 0 | 1 | 3 | 3 | | 0 | 0 | > -3 | disp - 1 | | 0 | 0 | -3 | -3 |
Constraints
- Use a synchronous active-high reset.
- Output
dispmust be exactly 3 bits wide using two's complement representation. - The accumulator must saturate at +3 and -3 without wrapping around.
Topics
Solve this problem
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