Serial Stream Multiplexer
Time division multiplexing allows multiple slow devices to share a single high-speed bus. Interleaving two serial streams into one doubles the effective data rate on the output wire without requiring additional routing resources.
The circuit continuously alternates between reading a bit from stream A and a bit from stream B. The internal selection state is controlled by a synchronous active-high reset rst. When rst is 1, the internal state resets to 0. When rst is 0, the internal state toggles on each clock cycle. The output Y routes A or B continuously based on this internal state.
| rst | Current State | Next State | Y | |-------|---------------|------------|-----| | 1 | X | 0 | A | | 0 | 0 | 1 | A | | 0 | 1 | 0 | B |
Constraints
- Implement the selection state using exactly one flip-flop.
- Use combinational logic to route the selected input to
Y. - The reset signal
rstmust be synchronous and active-high.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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