Full UART Receiver
Every microcontroller and embedded system relies on serial communication to bridge discrete components. The UART receiver deserializes incoming asynchronous bitstreams into parallel bytes by coordinating edge detection, bit counting, and shift registers.
Implement a standard 8-N-1 UART receiver. The system operates on a clock clk that matches the baud rate. The rx line idles high. A transaction begins when rx drops to 0 (the start bit). Over the next 8 clock cycles, the 8 data bits arrive LSB first. The transaction concludes with a stop bit where rx must equal 1.
Exactly one clock cycle after a valid stop bit is sampled, assert valid high for one cycle and drive the assembled byte on data_out. If the stop bit is missing (framing error), discard the data, remain in the idle state, and do not assert valid.
Constraints
- Use a synchronous active-high reset
rst. data_outmust hold its most recently received valid byte whilevalidis low.- Do not assert
validif the sampled stop bit is 0. - The system must immediately return to idle and be ready to accept a new start bit after a stop bit.
Topics
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