Parity Checker

MediumLogic CircuitBuild

Serial communication protocols rely on lightweight error detection to catch single-bit corruption during transmission. The parity checker is a standard physical layer mechanism that validates incoming frames by calculating parity on the fly.

The circuit maintains a running even parity calculation for an incoming serial payload synchronized to an implicit clock.

rst (1-bit): Synchronous active-high reset. Clears the internal parity state and the err output to 0.
data_in (1-bit): The incoming serial data stream.
en (1-bit): When high, the current data_in bit is accumulated into the running parity state.
check (1-bit): When high, data_in represents the received parity bit. If data_in does not match the accumulated payload parity, assert the err output to 1 on the next clock cycle.
err (1-bit): The parity error flag. Once asserted, it must remain high until the module is reset.

Constraints

Implement synchronous active-high reset logic for all state elements.
The err output must be registered.
Do not accumulate data_in into the parity state during the cycle when check is high.

Topics

Sequential LogicState MachinesError Detection

Solve this problem

Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Parity Checker

MediumLogic CircuitBuild

The circuit maintains a running even parity calculation for an incoming serial payload synchronized to an implicit clock.

rst (1-bit): Synchronous active-high reset. Clears the internal parity state and the err output to 0.
data_in (1-bit): The incoming serial data stream.
en (1-bit): When high, the current data_in bit is accumulated into the running parity state.
check (1-bit): When high, data_in represents the received parity bit. If data_in does not match the accumulated payload parity, assert the err output to 1 on the next clock cycle.
err (1-bit): The parity error flag. Once asserted, it must remain high until the module is reset.

Constraints

Implement synchronous active-high reset logic for all state elements.
The err output must be registered.
Do not accumulate data_in into the parity state during the cycle when check is high.

Topics

Sequential LogicState MachinesError Detection

Solve this problem

Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Parity Checker

Constraints

Topics

Solve this problem

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Parity Checker

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